1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device and, more particularly, to a method for forming a storage node contact opening for a dynamic random access memory (DRAM).
2. Description of the Related Art
In FIG. 1, a semiconductor substrate 10 is shown. A plurality of parallel gate electrode lines 20 with predetermined spacing, and a plurality of parallel bit lines 18 perpendicular to the gate electrode lines 20 and with predetermined spacing are arranged on the semiconductor substrate 10. Between each of the gate electrode lines 20 are conductive plugs (or landing pads) 12 for storage nodes (or conductive pads) 16 and conductive plugs 14 for a bit lines 18. Each of the storage nodes 16 is electrically connected through a buried contact (referred to below as a xe2x80x9cBCxe2x80x9d) to a conductive plug 12. Each of the bit lines 18 is electrically connected through a direct contact (referred to below as a xe2x80x9cDCxe2x80x9d) to a conductive plug 14. A memory cell formed on semiconductor substrate 10 comprises a storage node 16, a conductive plug 14 for a bit line 18, and an electrode line 20 interposed therebetween.
Referring to FIGS. 2A-2C, on the semiconductor substrate 10 are formed a conductive plug 14 (referred to below as a xe2x80x9cDC plugxe2x80x9d) that electrically connects a bit line 18 (referred to below as a xe2x80x9cBLxe2x80x9d) to the semiconductor substrate 10, and a conductive plug 12 (referred to below as a xe2x80x9cBC plugxe2x80x9d) that electrically connects a storage node 16 to the semiconductor substrate 10. After formation of a bit line 18, a contact opening (or contact hole) for forming a storage node 16 is formed. Then the storage node 16 is formed on the BC plug 12, as shown in FIG. 2A. The process steps required to form these features are well known to those skilled in the art.
As the integration level of a semiconductor device (in particular, a DRAM) formed on the semiconductor substrate 10 increases, the depth of the contact opening (for forming a storage node 16 to connect to a BC plug 12) increases and the diameter at the bottom of the contact opening decreases. The height of the contact opening increases in proportion to the decrease in the wiring width of bit line 18. It takes additional etching time to form a deeper contact opening to connect a storage node 16 to a BC plug 12. As a result, the contact opening is overetched so that the upper diameter of the contact opening increases.
If the increased diameter contact opening (i.e., the BC opening) is misaligned, the storage node 16 in the contact opening may be etched in a portion 22 during an etching process for forming the storage node 16. Thus, if a dielectric film (not shown) and a plate electrode (not shown) are formed on an overall surface of the semiconductor substrate 10, it may be impossible to insulate a storage node 16 from the plate electrode because the dielectric characteristics of the dielectric film may be degraded in the portion 22 that is misaligned as a result of overetching. In the worst case, the storage node 16 may fall down due to overetching. Furthermore, the deeper the contact opening is, the more difficult it is to clean an internal portion of the contact opening.
Following is a description of a technique which has been suggested to solve the foregoing problems. Referring to FIGS. 3A-3C, a DC opening is simultaneously formed on a BC formation region (conductive plug 12xe2x80x2 for a storage node) with a DC opening. The DC opening connects a bit line 18xe2x80x2 to a conductive plug 14xe2x80x2. After formation of bit line material on the overall surface of a semiconductor substrate 10, a bit line 18xe2x80x2 is formed using a conventional photo-etching process. At the same time, a plug 24 is also formed at the DC opening on the BC plug 12xe2x80x2 from the same material as the bit line 18xe2x80x2 by controlling the etching time of the bit line material, as shown in FIG. 3A.
Forming the plug 24 on the BC plug 12xe2x80x2 reduces the depth of the BC opening. As shown in FIG. 3A, the depth of the BC opening is reduced as much as the thickness D1 of an insulating layer 26. It is, however, still difficult to overcome the thickness D2 of the bit line 18xe2x80x2 and an interlayer insulating film 28 when the BC opening is formed. The prior problems may also occur when the BC contact opening and the storage node 16xe2x80x2 are formed.
The present invention provides a method for fabricating a semiconductor device capable of reducing the etching depth and the diameter of a contact opening. In particular, the invention provides a method for fabricating a storage node contact opening in a DRAM having a reduced depth and a reduced diameter of the contact opening.
According to one aspect of the present invention, one or more insulating layers are formed on a semiconductor substrate having a buried contact plug. The insulating layers are etched down to the buried contact plug to form a first contact opening on the buried contact plug. A photoresist pattern is formed on a top surface of the insulating layers and the first contact opening, and the insulating layers are etched using the photoresist pattern as a mask to form a second contact opening. The first and second contact openings are then filled with a conductive material.
The conductive material in the second contact opening may be a portion of a bit line, and the conductive material may be polysilicon, metal, or metal and polysilicon. The second contact opening preferably does not penetrate the insulating layers. The method may also include forming an additional insulating layer on the top surface of the semiconductor substrate, and etching the additional insulating layer down to the conductive material to form a contact opening on the conductive material for formation of a storage node. In addition, the step of filling the first and second contact openings with a conductive material may include forming the conductive material on a top surface of the insulating layers and the first and second contact openings, and etching the conductive material down to a top surface of the insulating layers.
According to another aspect of the present invention, a first, second, third, and fourth insulating layers are formed on an overall surface of a semiconductor substrate having a plurality of buried contact plugs. First contact openings are formed on the buried contact plugs by etching the fourth, third, second, and first insulating layers down to a top surface of the buried contact plugs. A photoresist pattern is formed on the fourth insulating layer and the first contact openings. Second contact openings are formed on the second insulating layer by etching the fourth and the third insulating layers using the photoresist pattern as a mask. Finally, the first and second contact openings are filled with conductive material.
The second and the fourth insulating layers are may be made of a nitride. The second insulating layer may be formed with a thickness of about 200 to 300 xc3x85, and the fourth insulating layer may be formed with a thickness of 500 xc3x85. The first and the third insulating layers may be made of an oxide. The first insulating layer may be formed with a thickness of 1,000 xc3x85, and the third insulating layer may be formed with a thickness of 2,000 xc3x85. The second insulating layer may serve as an etch-stop layer during formation of the second contact openings. The conductive material in the second contact opening may form a portion of a bit line, and may be polysilicon, metal, or metal and polysilicon.
The method may further include the steps of forming a fifth insulating layer on the overall surface of the semiconductor substrate, and etching the fifth insulating layer down the conductive material to form storage node contact openings on the conductive material. The conductive material may be etched through either an etchback process or a chemical mechanical polishing (CMP) process. The fourth insulating layer may serve as an etch-stop layer when the conductive material is etched.
According to yet another aspect of the present invention, one or more insulating layers are formed on a semiconductor substrate having a buried contact plug. A photoresist pattern is formed on a top surface of the insulating layers, and the insulating layers are etched, using the photoresist pattern as a mask, to form a first contact opening. The insulating layers are then etched down to the buried contact plug to form a second contact opening on the buried contact plug. Finally, the first and second contact openings are filled with a conductive material.
As a result, a conductive plug is formed on a buried contact plug together with a bit line, at the same time.